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BD6083GUL
Datasheet
● I/O
When the RESETB pin is Low, the input buffers (SDA and SCL) are disabling for the Low consumption power.
When RESETB=L, output is fixed at “H.”
SCL
Level shifter
(SDA)
EN
Logic
RESETB
Figure 20.
Special care should be taken because a current path may be formed via a terminal protection diode, depending on an I/O
power-on sequence or an input level.
● About the Start of LDO1 to LDO4
It must start as follows.
VBAT
T VBATON
T VBATOFF
VIO
T VIOON=min 0.1ms
T VIOOFF=min 1ms
RESETB
T RSTB=min 0.1ms
T RST=min 0ms
LDO1EN or LDO2EN or
LDO3EN or LDO4EN
T RISE = max 1ms
LDO1O or LDO2O or
LDO3O or LDO4O
(LDO output)
Figure 21.
<Start Sequence>
VBAT ON (Enough rise up) → VIO ON (Enough rise up) → Reset release → LDO ON (Register access acceptable)
<End Sequence>
LDO OFF → Reset → VIO OFF (Enough fall down) → VBAT OFF
● About the Pin Management of the Function that Isn't Used and Test Pins
Setting it as follows is recommended with the test pin and the pin which isn't used.
S et up pin referring to the “Equivalent circuit diagram” so that there may not be a problem under the actual use.
T2,T4
T1,T3
Non-used LED Pin
WPWMIN
Short to GND because pin for test input
OPEN because pin for test output
Short to GND (Must)
Don’t set the register concerned with non-used LED Pin
Short to ground
(A Pull-Down resistance built-in terminal is contained, too.)
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
35/42
TSZ02201-0G3G0C200100-1-2
05.Oct.2012 Rev.001
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